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2011 | 21 | 2 | 385-399

Tytuł artykułu

Energy characteristic of a processor allocator and a network-on-chip

Treść / Zawartość

Warianty tytułu

Języki publikacji

EN

Abstrakty

EN
Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

Słowa kluczowe

Rocznik

Tom

21

Numer

2

Strony

385-399

Opis fizyczny

Daty

wydano
2011
otrzymano
2010-05-12
poprawiono
2010-09-10

Twórcy

autor
  • Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, 4505 S. Maryland Parkway, Las Vegas, NV 89154-4026, USA
  • Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, 4505 S. Maryland Parkway, Las Vegas, NV 89154-4026, USA
  • Institute of Telecommunications, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland
  • Institute of Telecommunications, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland

Bibliografia

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  • Krishna, T., Kumarand, A., Chiang, P., Erez, M. and Peh, L.S. (2008). NoC with near-ideal express virtual channels using global-line communication, 16th IEEE Symposium on High Performance Interconnects, pp. 11-20, DOI: 10.1109/HOTI.2008.22.
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  • Su, C. and Shin, K.G. (1993). Adaptive deadlock-free routing in multicomputers using only one extra virtual channel, 1993 International Conference on Parallel Processing, Vol. 1, pp. 227-231, DOI: 10.1109/ICPP.1993.37.
  • Taylor, M., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, J.W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S. and Agarwal, A. (2002). The raw microprocessor: A computational fabric for software circuits and general-purpose programs, IEEE Micro 22(2): 25-35, DOI: 10.1109/MM.2002.997877.
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  • Zydek, D. and Selvaraj, H. (2009). Processor allocation problem for NoC-based chip multiprocessors, 6th International Conference on Information Technology: New Generations (ITNG 2009), Las Vegas, NV, USA, pp. 96-101, DOI: 10.1109/ITNG.2009.182.
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  • Zydek, D., Selvaraj, H. and Gewali, L. (2010). Synthesis of processor allocator for torus-based chip multiprocessors, 7th International Conference on Information Technology: New Generations (ITNG 2010), Las Vegas, NV, USA, pp. 13-18, DOI: 10.1109/ITNG.2010.145.
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Typ dokumentu

Bibliografia

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