Decomposition-based logic synthesis for PAL-based CPLDs

• Autorzy: Adam Opara , Dariusz Kania
• Języki publikacji: EN

Abstrakty

EN

The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

Słowa kluczowe

EN

decomposition; technology mapping; logic optimization; BDD; CPLD

• Wydawca: University of Zielona Gora Press
• Czasopismo: International Journal of Applied Mathematics and Computer Science
• Rocznik: 2010
• Tom: 20
• Numer: 2
• Strony: 367-384

Daty

wydano

2010

otrzymano

2009-07-13

poprawiono

2010-01-16

Twórcy

autor

Adam Opara

• Institute of Computer Science, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice

autor

Dariusz Kania

• Institute of Electronics, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice

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Identyfikatory

DOI

10.2478/v10006-010-0027-1