Reduction in the number of PAL macrocells in the circuit of a Moore FSM

• Autorzy: Alexander Barkalov , Larysa Titarenko , Sławomir Chmielewski
• Języki publikacji: EN

Abstrakty

EN

Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

Słowa kluczowe

EN

complex programmable logic devices; Moore finite-state machine; pseudoequivalent states; logic circuit; design

• Wydawca: University of Zielona Gora Press
• Czasopismo: International Journal of Applied Mathematics and Computer Science
• Rocznik: 2007
• Tom: 17
• Numer: 4
• Strony: 565-575

Daty

wydano

2007

otrzymano

2007-03-06

poprawiono

2007-08-30

(nieznana)

2007-10-27

Twórcy

autor

Alexander Barkalov

• Institute of Computer Engineering and Electronics, University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland

autor

Larysa Titarenko

• Institute of Computer Engineering and Electronics, University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland

autor

Sławomir Chmielewski

• Institute of Computer Engineering and Electronics, University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland

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