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Reduction in the number of PAL macrocells in the circuit of a Moore FSM

100%
Barkalov A., Titarenko L., Chmielewski S.
International Journal of Applied Mathematics and Computer Science
|
2007
|
tom 17
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nr 4
565-575
EN
Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.
2
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Design of mealy finite-state machines with the transformation of object codes

100%
Barkalov A. A., Alexander A. Barkalov, Jr.
International Journal of Applied Mathematics and Computer Science
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2005
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tom 15
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nr 1
151-158
EN
An optimization method of the logic circuit of a Mealy finite-state machine is proposed. It is based on the transformation of object codes. The objects of the Mealy FSM are internal states and sets of microoperations. The main idea is to express the states as some functions of sets of microoperations (internal states) and tags. The application of this method is connected with the use of a special code converter in the logic circuit of an FSM. An example of application is given. The effectiveness of the proposed method is also studied.
3
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Reduction in the number of LUT elements for control units with code sharing

86%
Barkalov A., Titarenko L., Bieganowski J.
International Journal of Applied Mathematics and Computer Science
|
2010
|
tom 20
|
nr 4
751-761
EN
Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.
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