Stability of the 4-2 Binary Addition Circuit Cells. Part I

• Autorzy: Katsumi Wasaki
• Języki publikacji: EN

Abstrakty

EN

To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuits (GFAs) that generalized adder to have for each positive and negative weights to inputs and outputs [15]. We then successfully prove its circuit stability of the calculation outputs after four-steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: FTACELL1, version: 7.9.03 4.108.1028

• Wydawca: De Gruyter Open
• Czasopismo: Formalized Mathematics
• Rocznik: 2008
• Tom: 16
• Numer: 4
• Strony: 377-387

Daty

wydano

2008-01-01

online

2009-03-20

Twórcy

autor

Katsumi Wasaki

• Shinshu University, Nagano, Japan

Bibliografia

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Identyfikatory

DOI

10.2478/v10037-008-0046-7