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2008 | 16 | 4 | 377-387
Tytuł artykułu

Stability of the 4-2 Binary Addition Circuit Cells. Part I

Autorzy
Treść / Zawartość
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuits (GFAs) that generalized adder to have for each positive and negative weights to inputs and outputs [15]. We then successfully prove its circuit stability of the calculation outputs after four-steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: FTACELL1, version: 7.9.03 4.108.1028
Słowa kluczowe
Wydawca
Rocznik
Tom
16
Numer
4
Strony
377-387
Opis fizyczny
Daty
wydano
2008-01-01
online
2009-03-20
Twórcy
  • Shinshu University, Nagano, Japan
Bibliografia
  • [1] Grzegorz Bancerek. König's theorem. Formalized Mathematics, 1(3):589-593, 1990.
  • [2] Grzegorz Bancerek and Yatsuka Nakamura. Full adder circuit. Part I. Formalized Mathematics, 5(3):367-380, 1996.
  • [3] Czesław Byliński. Functions and their basic properties. Formalized Mathematics, 1(1):55-65, 1990.
  • [4] Yatsuka Nakamura and Grzegorz Bancerek. Combining of circuits. Formalized Mathematics, 5(2):283-295, 1996.
  • [5] Yatsuka Nakamura, Piotr Rudnicki, Andrzej Trybulec, and Pauline N. Kawamoto. Introduction to circuits, II. Formalized Mathematics, 5(2):273-278, 1996.
  • [6] Yatsuka Nakamura, Piotr Rudnicki, Andrzej Trybulec, and Pauline N. Kawamoto. Preliminaries to circuits, II. Formalized Mathematics, 5(2):215-220, 1996.
  • [7] Takaya Nishiyama and Yasuho Mizuhara. Binary arithmetics. Formalized Mathematics, 4(1):83-86, 1993.
  • [8] Andrzej Trybulec. Enumerated sets. Formalized Mathematics, 1(1):25-34, 1990.
  • [9] Andrzej Trybulec. Many sorted algebras. Formalized Mathematics, 5(1):37-42, 1996.
  • [10] Zinaida Trybulec. Properties of subsets. Formalized Mathematics, 1(1):67-71, 1990.
  • [11] E. Jean Vuillemin. A very fast multiplication algorithm for VLSI implementation, integration. The VLSI Journal, 1(1):39-52, 1983.
  • [12] Katsumi Wasaki and Pauline N. Kawamoto. 2's complement circuit. Formalized Mathematics, 6(2):189-197, 1997.
  • [13] Edmund Woronowicz. Many-argument relations. Formalized Mathematics, 1(4):733-737, 1990.
  • [14] Edmund Woronowicz. Relations and their basic properties. Formalized Mathematics, 1(1):73-83, 1990.
  • [15] Shin'nosuke Yamaguchi, Katsumi Wasaki, and Nobuhiro Shimoi. Generalized full adder circuits (GFAs). Part I. Formalized Mathematics, 13(4):549-571, 2005.
Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.doi-10_2478_v10037-008-0046-7
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