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2017 | 27 | 1 | 207-222
Tytuł artykułu

Area-oriented technology mapping for LUT-based logic blocks

Treść / Zawartość
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.
Słowa kluczowe
Rocznik
Tom
27
Numer
1
Strony
207-222
Opis fizyczny
Daty
wydano
2017
otrzymano
2015-10-06
poprawiono
2016-04-01
poprawiono
2016-10-13
zaakceptowano
2016-10-24
Twórcy
  • Faculty of Mechanical Engineering and Computer Science, University of Bielsko-Biała, ul. Willowa 2, 43-309 Bielsko-Biała, Poland
  • Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
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Bibliografia
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