Synthesis of finite state machines for CPLDs

• Autorzy: Robert Czerwiński , Dariusz Kania
• Języki publikacji: EN

Abstrakty

EN

The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of twolevel minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

Słowa kluczowe

EN

logic synthesis; FSM; state assignment; logic optimization; CPLD

• Wydawca: University of Zielona Gora Press
• Czasopismo: International Journal of Applied Mathematics and Computer Science
• Rocznik: 2009
• Tom: 19
• Numer: 4
• Strony: 647-659

Daty

wydano

2009

otrzymano

2008-09-25

poprawiono

2009-03-14

poprawiono

2009-04-28

Twórcy

autor

Robert Czerwiński

• Institute of Electronics, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland

autor

Dariusz Kania

• Institute of Electronics, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland

Bibliografia

• Baranov, S. (1994). Logic Synthesis for Control Automata, Kluwer Academic Publishers, Dordrecht.
• Barkalov, A., Titarenko, L. and Chmielewski, S. (2007). Reduction in the number of PAL macrocells in the circuit of a Moore FSM, International Journal of Applied Mathematics and Computer Science 17(4): 565-575.
• Chattopadhyay, S. (2001). Low power state assignment and flipflop selection for finite state machine synthesis-A genetic algorithmic approach, IEE Proceedings-Computers and Digital Techniques 148(45): 147-151.
• Chyży, M. and Kłosiński, W. (2002). Evolutionary algorithm for state assignment of finite state machines, Proceedings of the Euromicro Symposium on Digital System Design, Dortmund, Germany, pp. 359-362.
• Czerwiński, R. and Kania, D. (2005). State assignment for PALbased CPLDs, Proceedings of the 8-th Euromicro Symposium on Digital System Design, DSD2005, Porto, Portugal, IEEE Computer Society Press, Porto, pp. 127-134.
• Czerwiński, R., Kania, D. and Kulisz, J. (2006). FSMs state encoding targeting at logic level minimization, Bulletin of the Polish Academy of Sciences 54(4): 479-487.
• Czerwiński, R. and Kulisz, J. (2009). State machine description oriented towards effective usage of vendor-independent synthesis tool, IFAC Workshop on Programmable Devices and Embedded Systems, PDES'2009, Roznov and Radhostem, Czech Republic, pp. 27-32.
• Czerwiński, R. (2006). The FSMs State Assignment for PALBased Matrix Programmable Structures, Ph.D. thesis, Silesian University of Technology, Gliwice, (in Polish).
• De Micheli, G. (1994). Synthesis and Optimization of Digital Circuits, McGraw-Hill Inc., New York, NY.
• Devadas, S. and Newton, A. R. (1991). Exact algorithms for output encoding, state assignment and four-level boolean minimization, IEEE Transactions on Computer-Aided Design 10(1): 13-27.
• Jóźwiak, L. and Volf, F. (1995). Efficient decomposition of assigned sequential machines and boolean functions for PLD implementations, Proceedings of Electronic Technology Directions to the Year 2000, Adelaide, Australia, pp. 258-266.
• Kania, D. (2003). An efficient approach to synthesis of multi-output boolean functions on PAL-based devices, IEE Proceedings on Computer and Digital Techniques 150(3): 143-149.
• Kania, D. (2004). The Logic Synthesis for the PAL-based Complex Programmable Logic Devices, Silesian University of Technology, Gliwice, (in Polish).
• MCNC (1991). LGSynth'91 benchmarks, Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, Raleigh, NC, http://www.cbl.ncsu.edu/.
• Mengibar, L., Entrena, L., M.G.Lorenz and E.S.Millan (2005). Patitioned state encoding for low power in FPGAs, Electronics Letters 41(17): 948-949.
• Park, S., Yang, S. and Cho, S. (2000). Optimal state assignment technique for partial scan designs, Electronics Letters 36(18): 1527-1529.
• Salauyou, V., Klimowicz, A., Grzes, T., Dimitrova-Grekow, T. and Bulatowa, I. (2006). Experimental Studies of Finite State Machines Synthesis Methods Implemented in Package ZUBR, Pomiary, Automatyka, Kontrola 52(6 bis): 44-46, (in Polish).
• Sentovich, E., Singh, K., Moon, C., Savoj, H., Brayton, R. and Sangiovanni-Vincentelli, A. (1992). SIS: A system for sequential circuit synthesis, Technical report, University of California, Berkeley, CA.
• Sharma, K. (1998). Programmable Logic Handbook, PLDs, CPLDs, & FPGAs, McGraw-Hill, New York, NY.
• Villa, T., Kam, T., Brayton, R. and Sangiovanni-Vincentelli, A. (1997). Synthesis of Finite State Machines: Logic Optimization, Kluwer Academic Publishers, Boston, MA.
• Villa, T. and Sangiovanni-Vincentelli, A. (1990). NOVA: State assignment for finite state machines for optimal two-level logic implementation, IEEE Transactions on ComputerAided Design 9(9): 905-924.
• Yang, S. and Ciesielski, M. (1991). Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization, IEEE Transactions on Computer-Aided Design 10(1): 4-12.

Identyfikatory

DOI

10.2478/v10006-009-0052-0