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2008 | 18 | 3 | 329-339
Tytuł artykułu

Address sequences and backgrounds with different Hamming distances for multiple run March tests

Treść / Zawartość
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
It is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.
Rocznik
Tom
18
Numer
3
Strony
329-339
Opis fizyczny
Daty
wydano
2008
otrzymano
2007-11-06
poprawiono
2008-04-10
Twórcy
  • Belarusian State University of Computer Science and Radioelectronics, P. Brovki 6, 220013 Minsk, Belarus
Bibliografia
  • Bernardi E., Sancez M., Squillero G. and Sonza Reorda M. (2006). An effective technique for minimizing the cost of processor software-based diagnosis in SoCs, Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, pp. 412-417.
  • Bernardi P., Grosso M., Rebaudengo M. and Sonza Reorda M. (2005). Exploiting an infrastructure IP to reduce the costs of memory diagnosis in SoCs, Proceedings of the European Test Symposium, Tallinn, Estonia, pp. 202-207.
  • Cheng K.-L., Tsai M.-F. and Wu C.-W. (2001). Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories, Proceedings of the IEEE VLSI Test Symposium (VTS), Marina del Rey, CA, USA, pp. 225-237.
  • Cheng K.-L., Tsai M.-F. and Wu C.-W. (2002). Neighborhood pattern sensitive fault testing and diagnostics for random access memories, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21(11): 1328-1336.
  • Cockburn B. E. (1995). Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs, Proceeding IEEE International Workshop on Memory Technology, Design and Testing (MTDT 95), San Jose, CA, USA, pp. 117-122.
  • Franklin M. and Saluja K. K. (1996). Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults, IEEE Transactions on Computer-Aided Design of Integrated Circuits 15(9): 1081-1087.
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  • Goor A. J. v. d. (1991). Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester.
  • Gray F. (1958). 2,632,058. Pulse code communication, U.S. Patent
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  • Niggemeyer D., Redeker M. and Otterstedt J. (1998). Integration of non-classical faults in standard march tests, Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, pp. 91-96.
  • Niggemeyer D., Redeker M. and Rudnick E. (2000). Diagnostic testing of embedded memories based on output tracing, Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, pp. 113-118.
  • Pomeranz I. and Reddy S. M. (2006). Fault detection by output response comparison of identical circuits using halffrequency compatible sequences, Proceedings of the International Test Conference, Santa Clara, CA, USA, pp. 202-207.
  • Savage C. (1997). A survey of combinatorial Gray codes, SIAM Review 39(4): 605-629.
  • Sokol B. and Yarmolik S. V. (2006). Address sequence for March tests to detect pattern sensitive faults, Proceedings of the 3rd IEEE International Workshop on Electronic Design Test & Applications (DELTA'06), Kuala Lumpur, Malaysia, pp. 354-357.
  • Suk D. S. and Reddy S. M. (1980). Test procedures for a class of pattern sensitive faults in semiconductor random access memories, IEEE Transactions on Computers 29(6): 419-429.
  • Yarmolik S. V. (2006). Gray code with maximum of Hamming distance, Proceedings of the 4th International SciencePractice Forum on Information Technologies and Cybernetics, Dnipropetrovsk, Ukraine, p. 77.
  • Yarmolik S. V. and Sokol B. (2006). Optimal memory address seeds for pattern sensitive faults detection, Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2006), Prague, Czech Republic, pp. 220-221.
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Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.bwnjournal-article-amcv18i3p329bwm
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