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2008 | 18 | 3 | 319-328
Tytuł artykułu

New self-checking Booth multipliers

Treść / Zawartość
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.
Rocznik
Tom
18
Numer
3
Strony
319-328
Opis fizyczny
Daty
wydano
2008
otrzymano
2007-01-25
poprawiono
2007-05-26
poprawiono
2008-05-09
Twórcy
autor
  • Department of Electrical Engineering and Computer Science, University of Paderborn, 33098 Paderborn, Germany
  • Department of Computer Science, University of Potsdam, 14415 Potsdam, Germany
Bibliografia
  • Al-Twaijry H. A. and Flynn M. J. (1995). Performance/area tradeoffs in Booth multipliers, Technical Report CSL-TR-95684, Stanford University.
  • Booth A. D. (1951). A signed binary multiplication technique, The Quarterly Journal of Mechanics and Applied Mathematics 4(2): 236-240.
  • Goessel M. and Graf F. (1993). Error Detection Circuits, McGraw-Hill, London.
  • Gorshe S. S. and Bose B. (1996). A self-checking ALU design with efficient codes, Proceedings of the 14th IEEE VLSI Test Symposium (VTS '96), IEEE Computer Society, Washington, DC, USA, p. 157.
  • Hsiao M. and Sellers F. (1963). The carry dependent sum adder, IEEE Transactions on Electronic Computers, EC-12: 265-268.
  • Hunger M. (2006). Self-checking Booth-3 multiplier, Proceedings of the 1st International Conference for Young Researchers in Computer Science, Control, Electrical Engineering and Telecommunications, Zielona Góra, Poland.
  • Lala P. (Ed.) (2001). Self-Checking and Fault-Tolerant Tigital Tesign, Morgan Kaufmann Publishers Inc., San Francisco, CA.
  • Lo J. C., Thanawastien S. and Rao T. R. N. (1993). Berger check prediction for array multipliers and array dividers, IEEE Transactions on Computers 42(7): 892-896.
  • Marienfeld D., Sogomonyan E. S., Ocheretnij V. and Gossel M. (2004). A new self-checking multiplier by use of a codedisjoint sum-bit duplicated adder, Proceedings of the 9th IEEE European Test Symposium (ETS'04), IEEE Computer Society, Washington, DC, USA, pp. 30-35.
  • Marienfeld D., Sogomonyan E. S., Ocheretnij V. and Gossel M. (2005). New self-checking output-duplicated booth multiplier with high fault coverage for soft errors, ATS '05: Proceedings of the 14th Asian Test Symposium, IEEE Computer Society, Los Alamitos, CA, USA, pp. 76-81.
  • Nicolaidis M. and Duarte R. O. (1998). Design of faultsecure parity-prediction booth multipliers, Proceedings of the Conference on Design, Automation and Test in Europe (DATE '98), IEEE Computer Society, Washington, DC, USA, pp. 7-14.
  • Nicolaidis M., Duarte R. O., Manich S. and Figueras, J. (1997). Fault-secure parity prediction arithmetic operators, IEEE Design and Test 14(2): 60-71.
  • Ocheretnij V., Sogomonya E. S. and Goessel M. (2001). A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes, Proceedings of the 10th Asian Test Symposium (ATS '01), IEEE Computer Society, Los Alamitos, CA, USA, pp. 365.
  • Parhami B. (2001). Instructor's manual for 'Computer Arithmetic: Algorithms and Hardware Designs', Vol. 2: Presentation Material, Oxford University Press, Oxford.
  • Shivakumar P., Keckler S. W., Kistler M., Burger D. and Alvisi L. (2002). Modeling the effect of technology trends on the soft error rate of combinatorial logic, Proceedings of the International Conference on Dependable Systems and Networks, pp. 389-398.
  • Sparmann U. and Reddy S. M. (1994). On the effectiveness of residue code checking for parallel two's complement multipliers, Proceedings of the 24th International Symposium on Fault Tolerant Computing FTCS-24, IEEE Computer Society Press, Austin, TX, USA, pp. 219-229.
  • Sulistyo J. B. and Ha D. S. (2002). A new characterization method for delay and power dissipation of standard cells, VLSI Design 15(3): 667-678.
Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.bwnjournal-article-amcv18i3p319bwm
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