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2006 | 16 | 4 | 525-535
Tytuł artykułu

Pipelined architectures for the Frequency Domain linear equalizer

Treść / Zawartość
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simulation results are presented that illustrate the performance of the effect of the time delay introduced into the adaptation algorithm. The proposed architectures for efficient pipelining of the FD LMS linear equalization algorithm are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.
Rocznik
Tom
16
Numer
4
Strony
525-535
Opis fizyczny
Daty
wydano
2006
otrzymano
2005-10-08
poprawiono
2006-09-16
Twórcy
  • Department of Telecommunications, University of Peloponnese, Terma Karaiskaki 22100, Tripoli, Greece
  • Department of Telecommunications, University of Peloponnese, Terma Karaiskaki 22100, Tripoli, Greece
Bibliografia
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Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.bwnjournal-article-amcv16i4p525bwm
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